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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-01-30 03:23:17 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-02-08 07:57:27 +0100 |
| commit | 656188ddc4075eb50260607b3497589873f373d2 (patch) | |
| tree | 5aa67ce17a83c22ec92727c898475f4026929d38 /clang/lib/Sema/SemaModule.cpp | |
| parent | 3304d51b676ea511feca28089cb60eba3873132e (diff) | |
| download | llvm-656188ddc4075eb50260607b3497589873f373d2.zip llvm-656188ddc4075eb50260607b3497589873f373d2.tar.gz llvm-656188ddc4075eb50260607b3497589873f373d2.tar.bz2 | |
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs. It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBs is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Depends on D143394
Differential Revision: https://reviews.llvm.org/D143036
Diffstat (limited to 'clang/lib/Sema/SemaModule.cpp')
0 files changed, 0 insertions, 0 deletions