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| author | eopXD <yueh.ting.chen@gmail.com> | 2023-06-13 18:35:14 -0700 |
|---|---|---|
| committer | eopXD <yueh.ting.chen@gmail.com> | 2023-06-20 11:09:24 -0700 |
| commit | 9ed668ad93218ab2fe062c977d89f486056b4e56 (patch) | |
| tree | 56eaa8ea0ac86605db463328205af790a72c2245 /clang/lib/Sema/SemaChecking.cpp | |
| parent | 5510f0b8f4b1400905194f0c75acb41c6b1c21ce (diff) | |
| download | llvm-9ed668ad93218ab2fe062c977d89f486056b4e56.zip llvm-9ed668ad93218ab2fe062c977d89f486056b4e56.tar.gz llvm-9ed668ad93218ab2fe062c977d89f486056b4e56.tar.bz2 | |
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
Depends on D151397.
This patch follows the patch-set of D151395. This patch seeks to
update all the remaining fixed-point intrinsics to model vxrm
control, adding rounding mode control for `vsmul`, `vssra`,
`vssrl`, `vnclip`, and `vnclipu`.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D152879
Diffstat (limited to 'clang/lib/Sema/SemaChecking.cpp')
| -rw-r--r-- | clang/lib/Sema/SemaChecking.cpp | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 3367fda..b652f25 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -4702,6 +4702,16 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vasubu_vx_ta: case RISCVVector::BI__builtin_rvv_vasub_vv_ta: case RISCVVector::BI__builtin_rvv_vasub_vx_ta: + case RISCVVector::BI__builtin_rvv_vsmul_vv_ta: + case RISCVVector::BI__builtin_rvv_vsmul_vx_ta: + case RISCVVector::BI__builtin_rvv_vssra_vv_ta: + case RISCVVector::BI__builtin_rvv_vssra_vx_ta: + case RISCVVector::BI__builtin_rvv_vssrl_vv_ta: + case RISCVVector::BI__builtin_rvv_vssrl_vx_ta: + case RISCVVector::BI__builtin_rvv_vnclip_wv_ta: + case RISCVVector::BI__builtin_rvv_vnclip_wx_ta: + case RISCVVector::BI__builtin_rvv_vnclipu_wv_ta: + case RISCVVector::BI__builtin_rvv_vnclipu_wx_ta: return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3); case RISCVVector::BI__builtin_rvv_vaaddu_vv_tu: case RISCVVector::BI__builtin_rvv_vaaddu_vx_tu: @@ -4711,6 +4721,16 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vasubu_vx_tu: case RISCVVector::BI__builtin_rvv_vasub_vv_tu: case RISCVVector::BI__builtin_rvv_vasub_vx_tu: + case RISCVVector::BI__builtin_rvv_vsmul_vv_tu: + case RISCVVector::BI__builtin_rvv_vsmul_vx_tu: + case RISCVVector::BI__builtin_rvv_vssra_vv_tu: + case RISCVVector::BI__builtin_rvv_vssra_vx_tu: + case RISCVVector::BI__builtin_rvv_vssrl_vv_tu: + case RISCVVector::BI__builtin_rvv_vssrl_vx_tu: + case RISCVVector::BI__builtin_rvv_vnclip_wv_tu: + case RISCVVector::BI__builtin_rvv_vnclip_wx_tu: + case RISCVVector::BI__builtin_rvv_vnclipu_wv_tu: + case RISCVVector::BI__builtin_rvv_vnclipu_wx_tu: case RISCVVector::BI__builtin_rvv_vaaddu_vv_tama: case RISCVVector::BI__builtin_rvv_vaaddu_vx_tama: case RISCVVector::BI__builtin_rvv_vaadd_vv_tama: @@ -4719,6 +4739,16 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vasubu_vx_tama: case RISCVVector::BI__builtin_rvv_vasub_vv_tama: case RISCVVector::BI__builtin_rvv_vasub_vx_tama: + case RISCVVector::BI__builtin_rvv_vsmul_vv_tama: + case RISCVVector::BI__builtin_rvv_vsmul_vx_tama: + case RISCVVector::BI__builtin_rvv_vssra_vv_tama: + case RISCVVector::BI__builtin_rvv_vssra_vx_tama: + case RISCVVector::BI__builtin_rvv_vssrl_vv_tama: + case RISCVVector::BI__builtin_rvv_vssrl_vx_tama: + case RISCVVector::BI__builtin_rvv_vnclip_wv_tama: + case RISCVVector::BI__builtin_rvv_vnclip_wx_tama: + case RISCVVector::BI__builtin_rvv_vnclipu_wv_tama: + case RISCVVector::BI__builtin_rvv_vnclipu_wx_tama: return SemaBuiltinConstantArgRange(TheCall, 3, 0, 3); case RISCVVector::BI__builtin_rvv_vaaddu_vv_tum: case RISCVVector::BI__builtin_rvv_vaaddu_vv_tumu: @@ -4744,6 +4774,36 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vasub_vx_tum: case RISCVVector::BI__builtin_rvv_vasub_vx_tumu: case RISCVVector::BI__builtin_rvv_vasub_vx_mu: + case RISCVVector::BI__builtin_rvv_vsmul_vv_mu: + case RISCVVector::BI__builtin_rvv_vsmul_vx_mu: + case RISCVVector::BI__builtin_rvv_vssra_vv_mu: + case RISCVVector::BI__builtin_rvv_vssra_vx_mu: + case RISCVVector::BI__builtin_rvv_vssrl_vv_mu: + case RISCVVector::BI__builtin_rvv_vssrl_vx_mu: + case RISCVVector::BI__builtin_rvv_vnclip_wv_mu: + case RISCVVector::BI__builtin_rvv_vnclip_wx_mu: + case RISCVVector::BI__builtin_rvv_vnclipu_wv_mu: + case RISCVVector::BI__builtin_rvv_vnclipu_wx_mu: + case RISCVVector::BI__builtin_rvv_vsmul_vv_tum: + case RISCVVector::BI__builtin_rvv_vsmul_vx_tum: + case RISCVVector::BI__builtin_rvv_vssra_vv_tum: + case RISCVVector::BI__builtin_rvv_vssra_vx_tum: + case RISCVVector::BI__builtin_rvv_vssrl_vv_tum: + case RISCVVector::BI__builtin_rvv_vssrl_vx_tum: + case RISCVVector::BI__builtin_rvv_vnclip_wv_tum: + case RISCVVector::BI__builtin_rvv_vnclip_wx_tum: + case RISCVVector::BI__builtin_rvv_vnclipu_wv_tum: + case RISCVVector::BI__builtin_rvv_vnclipu_wx_tum: + case RISCVVector::BI__builtin_rvv_vsmul_vv_tumu: + case RISCVVector::BI__builtin_rvv_vsmul_vx_tumu: + case RISCVVector::BI__builtin_rvv_vssra_vv_tumu: + case RISCVVector::BI__builtin_rvv_vssra_vx_tumu: + case RISCVVector::BI__builtin_rvv_vssrl_vv_tumu: + case RISCVVector::BI__builtin_rvv_vssrl_vx_tumu: + case RISCVVector::BI__builtin_rvv_vnclip_wv_tumu: + case RISCVVector::BI__builtin_rvv_vnclip_wx_tumu: + case RISCVVector::BI__builtin_rvv_vnclipu_wv_tumu: + case RISCVVector::BI__builtin_rvv_vnclipu_wx_tumu: return SemaBuiltinConstantArgRange(TheCall, 4, 0, 3); case RISCV::BI__builtin_riscv_ntl_load: case RISCV::BI__builtin_riscv_ntl_store: |