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authorCraig Topper <craig.topper@sifive.com>2023-12-28 10:48:50 -0800
committerCraig Topper <craig.topper@sifive.com>2023-12-28 11:15:14 -0800
commit8076ee9667198c28cfd1ef6dc8f01c3e539549a2 (patch)
treef8d5bd82640855056dbe011e76766f2d61c41622 /clang/lib/Sema/SemaChecking.cpp
parent5c37e711df6b81c2b669fb8a0d8b15f7a79e6e4a (diff)
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[RISCV] Use getBuiltinVectorTypeInfo instead of isRVVType.
I'm trying to remove all uses of isRVVType. Fix diagnostic message to report an error for the builtin instead of the type. Though I can't seem to get a test to hit it.
Diffstat (limited to 'clang/lib/Sema/SemaChecking.cpp')
-rw-r--r--clang/lib/Sema/SemaChecking.cpp14
1 files changed, 8 insertions, 6 deletions
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 2e61daf..da0570b 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5388,15 +5388,17 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
QualType Op1Type = TheCall->getArg(0)->getType();
QualType Op2Type = TheCall->getArg(1)->getType();
QualType Op3Type = TheCall->getArg(2)->getType();
- uint64_t ElemSize = Op1Type->isRVVType(32, false) ? 32 : 64;
+ ASTContext::BuiltinVectorTypeInfo Info =
+ Context.getBuiltinVectorTypeInfo(Op1Type->castAs<BuiltinType>());
+ uint64_t ElemSize = Context.getTypeSize(Info.ElementType);
if (ElemSize == 64 && !TI.hasFeature("zvknhb"))
return Diag(TheCall->getBeginLoc(),
- diag::err_riscv_type_requires_extension)
- << Op1Type << "zvknhb";
+ diag::err_riscv_builtin_requires_extension)
+ << /* IsExtension */ true << TheCall->getSourceRange() << "zvknb";
- return CheckInvalidVLENandLMUL(TI, TheCall, *this, Op1Type, ElemSize << 2) ||
- CheckInvalidVLENandLMUL(TI, TheCall, *this, Op2Type, ElemSize << 2) ||
- CheckInvalidVLENandLMUL(TI, TheCall, *this, Op3Type, ElemSize << 2);
+ return CheckInvalidVLENandLMUL(TI, TheCall, *this, Op1Type, ElemSize * 4) ||
+ CheckInvalidVLENandLMUL(TI, TheCall, *this, Op2Type, ElemSize * 4) ||
+ CheckInvalidVLENandLMUL(TI, TheCall, *this, Op3Type, ElemSize * 4);
}
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf8: