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| author | eopXD <yueh.ting.chen@gmail.com> | 2023-06-29 07:41:46 -0700 |
|---|---|---|
| committer | eopXD <yueh.ting.chen@gmail.com> | 2023-07-13 00:35:36 -0700 |
| commit | 474e37c113ac4ba989ed978e30b38c48c08d92b8 (patch) | |
| tree | 980acae47bf05cddfff9826eb80d1c4783a2c30e /clang/lib/Sema/SemaChecking.cpp | |
| parent | 76482078cdd2dca1f553904a1d2092626ba12856 (diff) | |
| download | llvm-474e37c113ac4ba989ed978e30b38c48c08d92b8.zip llvm-474e37c113ac4ba989ed978e30b38c48c08d92b8.tar.gz llvm-474e37c113ac4ba989ed978e30b38c48c08d92b8.tar.bz2 | |
[1/8][RISCV] Add rounding mode control variant for vfsub, vfrsub
Depends on D152996.
This patch-set aims to add a variant for the RVV floating-point
intrinsics that controls the rounding mode (`frm`). The rounding mode
variant appends `_rm` before the policy suffix to distinguish from
those without them.
Specification PR: riscv-non-isa/rvv-intrinsic-doc#226
This is the 1st patch of the patch-set.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D154628
Diffstat (limited to 'clang/lib/Sema/SemaChecking.cpp')
| -rw-r--r-- | clang/lib/Sema/SemaChecking.cpp | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 7f0fed4..dc0616b 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -4810,18 +4810,36 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, return SemaBuiltinConstantArgRange(TheCall, 4, 0, 3); case RISCVVector::BI__builtin_rvv_vfadd_vv_rm: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm: + case RISCVVector::BI__builtin_rvv_vfsub_vv_rm: + case RISCVVector::BI__builtin_rvv_vfsub_vf_rm: + case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm: return SemaBuiltinConstantArgRange(TheCall, 2, 0, 4); case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu: + case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tu: + case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tu: + case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tu: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tama: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tama: + case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tama: + case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tama: + case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tama: return SemaBuiltinConstantArgRange(TheCall, 3, 0, 4); case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum: + case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum: + case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tum: + case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu: + case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu: + case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tumu: + case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu: + case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu: + case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_mu: + case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_mu: return SemaBuiltinConstantArgRange(TheCall, 4, 0, 4); case RISCV::BI__builtin_riscv_ntl_load: case RISCV::BI__builtin_riscv_ntl_store: |