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| author | eopXD <yueh.ting.chen@gmail.com> | 2023-07-06 10:48:58 -0700 |
|---|---|---|
| committer | eopXD <yueh.ting.chen@gmail.com> | 2023-07-13 00:55:10 -0700 |
| commit | 2c38d6332345eddb7ed0509052383dc12faef767 (patch) | |
| tree | e9be0bb2c9cc9ddba9610618e3c7751ba1d0adfe /clang/lib/Sema/SemaChecking.cpp | |
| parent | 5d18d43f26ad8c0636c20008cd0ca855940c4a3d (diff) | |
| download | llvm-2c38d6332345eddb7ed0509052383dc12faef767.zip llvm-2c38d6332345eddb7ed0509052383dc12faef767.tar.gz llvm-2c38d6332345eddb7ed0509052383dc12faef767.tar.bz2 | |
[8/8][RISCV] Add rounding mode control variant for vfredosum, vfredusum, vfwredosum, vfwredusum
Depends on D154635
For the cover letter of the patch-set, please checkout D154628.
This is the 8th patch of the patch-set.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D154636
Diffstat (limited to 'clang/lib/Sema/SemaChecking.cpp')
| -rw-r--r-- | clang/lib/Sema/SemaChecking.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 693ff52..d0680b1 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -4842,6 +4842,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm: case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm: case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm: + case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm: + case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm: + case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm: + case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm: case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tu: case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tu: case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tu: @@ -4889,6 +4893,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tu: case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tu: case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tu: + case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tu: + case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tu: + case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tu: + case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tu: case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm: case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm: case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm: @@ -4957,6 +4965,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tama: case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tama: case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tama: + case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tama: + case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tama: + case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tama: + case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tama: case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tum: case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tum: case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tum: @@ -5065,6 +5077,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tum: case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tum: + case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tum: + case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tum: + case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tum: + case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tum: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu: |