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| author | Craig Topper <craig.topper@sifive.com> | 2020-11-04 11:37:58 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2020-11-04 11:37:58 -0800 |
| commit | cc3bf270776bc362e4a504a2f1bc3c8c932111ea (patch) | |
| tree | b5125ce7d58cd61f7a69c813cead899548280a15 /clang/lib/Lex/ModuleMap.cpp | |
| parent | 2e73a1f9faafe0a9bc6f8f177d7e92d8e6ae06b3 (diff) | |
| download | llvm-cc3bf270776bc362e4a504a2f1bc3c8c932111ea.zip llvm-cc3bf270776bc362e4a504a2f1bc3c8c932111ea.tar.gz llvm-cc3bf270776bc362e4a504a2f1bc3c8c932111ea.tar.bz2 | |
[RISCV] Remove assertsexti32 from fslw/fsrw isel patterns.
The operations in these patterns shouldn't be effected by sign
bits. And the pattern is starting from a sign_extend_inreg so
we aren't expecting sign bits to be passed through either.
Differential Revision: https://reviews.llvm.org/D90739
Diffstat (limited to 'clang/lib/Lex/ModuleMap.cpp')
0 files changed, 0 insertions, 0 deletions