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| author | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2022-04-17 17:44:39 +0530 |
|---|---|---|
| committer | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2022-12-17 11:48:44 +0530 |
| commit | 5ebe91fcb2a19ca58bb7a2ef97e8a33a85f3ce77 (patch) | |
| tree | 7ec2a677a171fda6d1ac7ba56e740f279d2a8ed3 /clang/lib/Lex/ModuleMap.cpp | |
| parent | af5e5c40ff73ca66e699c271e602a451a4d586a8 (diff) | |
| download | llvm-5ebe91fcb2a19ca58bb7a2ef97e8a33a85f3ce77.zip llvm-5ebe91fcb2a19ca58bb7a2ef97e8a33a85f3ce77.tar.gz llvm-5ebe91fcb2a19ca58bb7a2ef97e8a33a85f3ce77.tar.bz2 | |
[AMDGPU] Correctly set IsKill flag for VGPR spills in the prolog
We always assume the vector register is dead or killed while
inserting the VGPR spills in the prolog. It is not always
true. Used the entry block liveIn data while setting the flag.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D124194
Diffstat (limited to 'clang/lib/Lex/ModuleMap.cpp')
0 files changed, 0 insertions, 0 deletions