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| author | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2022-06-13 18:42:02 +0530 |
|---|---|---|
| committer | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2022-12-17 11:11:42 +0530 |
| commit | 5692a7e84e1273921099f9fbbaf353cd000df9bb (patch) | |
| tree | 3acef8bd9405e56da564a732a148b5e447aa578e /clang/lib/Lex/ModuleMap.cpp | |
| parent | cc037e17907dadc5ecb06bce61ce48a6627b274d (diff) | |
| download | llvm-5692a7e84e1273921099f9fbbaf353cd000df9bb.zip llvm-5692a7e84e1273921099f9fbbaf353cd000df9bb.tar.gz llvm-5692a7e84e1273921099f9fbbaf353cd000df9bb.tar.bz2 | |
[AMDGPU] Callee must always spill writelane VGPRs
Since the writelane instruction used for SGPR spills can
modify inactive lanes, the callee must preserve the VGPR
this instruction modifies even if it was marked Caller-saved.
Reviewed By: arsenm, nhaehnle
Differential Revision: https://reviews.llvm.org/D124192
Diffstat (limited to 'clang/lib/Lex/ModuleMap.cpp')
0 files changed, 0 insertions, 0 deletions