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authorCraig Topper <craig.topper@sifive.com>2022-03-22 09:53:39 -0700
committerCraig Topper <craig.topper@sifive.com>2022-03-22 10:14:43 -0700
commit9b0f227d7b2cee4e4492d0501e032f9b33579853 (patch)
tree146677e0c35d427810f5c6368a19a5621e8d325f /clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
parent23d60ce164db48cfaff84967e86dd052801bf73a (diff)
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[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
The mask being NoRegister prevented the existing aliases from matching since NoRegister isn't in the VMV0 register class. To workaround this I've added new aliases that look for zero_reg. I had to motify tablegen to generate matching code for zero_reg. And as a consequence, I had to change the EmitPriority for an ARM alias that used zero_reg that started printing. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D121496
Diffstat (limited to 'clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp')
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