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| author | guan jian <guanjian@stu.cdut.edu.cn> | 2025-11-11 11:03:34 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-11-10 19:03:34 -0800 |
| commit | 3618ed14e4b0461f6a060db04c4a06db402861cd (patch) | |
| tree | a23c825aa4383fe3c0df46b0e839780be57ae97e /clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp | |
| parent | 19d472f06efe4c744ef499d8bf3db740a2b9e2fb (diff) | |
| download | llvm-3618ed14e4b0461f6a060db04c4a06db402861cd.zip llvm-3618ed14e4b0461f6a060db04c4a06db402861cd.tar.gz llvm-3618ed14e4b0461f6a060db04c4a06db402861cd.tar.bz2 | |
[DAGCombiner] Add sra-xor-sra pattern fold (#166777)
Add `fold (sra (xor (sra x, c1), -1), c2) -> (sra (xor x, -1), c3)`
The IR like this:
```
%a = ashr i8 %x, 6
%n = xor i8 %a, -1
%s = sext i8 %n to i16
%r = and i16 %s, %y
ret i16 %r
```
llvm will produce:
```
slli a0, a0, 56
srai a0, a0, 56
not a0, a0
srai a0, a0, 6
and a0, a0, a1
ret
```
56 and 6 can be add up
alive2: https://alive2.llvm.org/ce/z/yxRQf9
---------
Co-authored-by: rez5427 <785369607@qq.com>
Diffstat (limited to 'clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions