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author | Craig Topper <craig.topper@sifive.com> | 2022-03-16 13:57:21 -0700 |
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committer | Craig Topper <craig.topper@sifive.com> | 2022-03-16 14:54:34 -0700 |
commit | 2e10671ec743c1ce5b237a6d8aff0c0c074a001d (patch) | |
tree | 34500465286437f546cdf0befb9afa2479e005d8 /clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp | |
parent | 50f82e68470c3efbb8ceae8f8c8d289a079d7031 (diff) | |
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[RISCV] Improve detection of when to skip (and (srl x, c2) c1) -> (srli (slli x, c3-c2), c3) isel.
We have a special case to skip this transform if c1 is 0xffffffff
and x is sext_inreg in order to use sraiw+zext.w. But we were only
checking that we have a sext_inreg opcode, not how many bits are
being sign extended.
This commit adds a check that it is a sext_inreg from i32 so we know for
sure that an sraiw can be created.
Diffstat (limited to 'clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions