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authorTom Stellard <thomas.stellard@amd.com>2013-11-27 21:23:35 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-11-27 21:23:35 +0000
commitc149dc02d36d1d4ed210b460f947dc5a3651454c (patch)
tree7df11ea1f7be99b990ca4ed14ca25c11e19b0a75 /clang/lib/Frontend/InitPreprocessor.cpp
parent859199dad89cefbf2c42962afccd07e532f1cc7f (diff)
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R600/SI: Implement spilling of SGPRs v5
SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions. v2: - Fix encoding of Lane Mask - Use correct register flags, so we don't overwrite the low dword when restoring multi-dword registers. v3: - Register spilling seems to hang the GPU, so replace all shaders that need spilling with a dummy shader. v4: - Fix *LANE definitions - Change destination reg class for 32-bit SMRD instructions v5: - Remove small optimization that was crashing Serious Sam 3. https://bugs.freedesktop.org/show_bug.cgi?id=68224 https://bugs.freedesktop.org/show_bug.cgi?id=71285 NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195880
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