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| author | Craig Topper <craig.topper@sifive.com> | 2022-11-30 10:28:55 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-11-30 10:28:57 -0800 |
| commit | a8c79121bf4da9155a2d8597c1fdef2796efc55b (patch) | |
| tree | dfb757171b6eaff720e38252b628d0e3e079001b /clang/lib/Frontend/InitPreprocessor.cpp | |
| parent | 6cca6b9ab9ff27d22cdb4b9b4aa98ec91b6b08d8 (diff) | |
| download | llvm-a8c79121bf4da9155a2d8597c1fdef2796efc55b.zip llvm-a8c79121bf4da9155a2d8597c1fdef2796efc55b.tar.gz llvm-a8c79121bf4da9155a2d8597c1fdef2796efc55b.tar.bz2 | |
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
Similar to previous patches for ADDI/ADDIW/SLLI/ADD, but restricted
to only cases where the register is x8-x15(GPRC reg class).
I've restricted it so that we can be precise about whether the
resulting instruction would be compressible. Changing the register
allocation may make some other instruction not compressible so we
should try to be accurate.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D138740
Diffstat (limited to 'clang/lib/Frontend/InitPreprocessor.cpp')
0 files changed, 0 insertions, 0 deletions