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authorBushev Dmitry <111585886+dybv-sc@users.noreply.github.com>2024-12-18 18:41:27 +0300
committerGitHub <noreply@github.com>2024-12-18 18:41:27 +0300
commit6993d32c77a78ac0e6eee0e4bffd714a455e776b (patch)
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parent76714be5fd4ace66dd9e19ce706c2e2149dd5716 (diff)
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[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120419)
This patch also makes following amendments to core exegesis: * Added distinction between regular registers aliasing check and registers used as memory address in instruction. * Added scratch memory space pointer register. * General exegesis options were amended: * mattr - new option to pass a list of enabled target features Llvm-exegesis RISCV port is a result of team effort. Below everyone involved listed. Co-authored-by: Konstantin Vladimirov <konstantin.vladimirov@syntacore.com> Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com> Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com> Co-authored-by: Mark Goncharov <mark.goncharov@syntacore.com> Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com> --------- Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
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