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author | Mészáros Gergely <gergely.meszaros@intel.com> | 2025-10-09 09:05:04 +0200 |
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committer | GitHub <noreply@github.com> | 2025-10-09 09:05:04 +0200 |
commit | cc1ca591a4bb2207ebe8b8f400ce0dbf3df43ff7 (patch) | |
tree | 1c8b64b31b8a681d5db440d12e563396513dc09c /clang/lib/Frontend/CompilerInvocation.cpp | |
parent | fb37929414abe02a5eefa040a0e24c0ea965ffdb (diff) | |
download | llvm-cc1ca591a4bb2207ebe8b8f400ce0dbf3df43ff7.zip llvm-cc1ca591a4bb2207ebe8b8f400ce0dbf3df43ff7.tar.gz llvm-cc1ca591a4bb2207ebe8b8f400ce0dbf3df43ff7.tar.bz2 |
[GlobalIsel] Add failure memory order to LegalityQuery (NFC) (#162284)
The `cmpxchg` instruction has two memory orders, one for success and one
for failure.
Prior to this patch `LegalityQuery` only exposed a single memory order,
that of the success case. This meant that it was not generally possible
to legalize `cmpxchg` instructions based on their memory orders.
Add a `FailureOrdering` field to `LegalityQuery::MemDesc`; it is only
set for `cmpxchg` instructions, otherwise it is `NotAtomic`. I didn't
rename `Ordering` to `SuccessOrdering` or similar to avoid breaking
changes for out of tree targets.
The new field does not increase `sizeof(MemDesc)`, it falls into
previous padding bits due to alignment, so I'd expect there to be no
performance impact for this change.
Verified no breakage via check-llvm in build with AMDGPU, AArch64, and X86 targets
enabled.
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions