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| author | Hari Limaye <hari.limaye@arm.com> | 2025-09-16 11:42:28 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-16 11:42:28 +0100 |
| commit | c6c60e1ec2c83bb12107160a90f31b6eeafbf7bf (patch) | |
| tree | 185d29e1405f8ef4533ee006eb39f645f8556880 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 7936b6f1133516c427c478104606d9276da6f81b (diff) | |
| download | llvm-c6c60e1ec2c83bb12107160a90f31b6eeafbf7bf.zip llvm-c6c60e1ec2c83bb12107160a90f31b6eeafbf7bf.tar.gz llvm-c6c60e1ec2c83bb12107160a90f31b6eeafbf7bf.tar.bz2 | |
[AArch64] Combine signext_inreg of setcc(... != splat(0)) (#157665)
Add the following fold AArch64 DAGCombine:
Fold setcc_merge_zero(
pred, insert_subvector(undef, signext_inreg(vNi1), 0),
!= splat(0))
-> setcc_merge_zero(pred, insert_subvector(undef, shl(vNi1), 0),
!= splat(0))
as the comparison (!= 0) depends only on bit 0 of the input, the left
shift is sufficient.
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions