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| author | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-05-01 10:26:47 +0000 |
|---|---|---|
| committer | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-05-01 10:26:47 +0000 |
| commit | a2861db834d909fc4ab3b5e5385ae24024520a97 (patch) | |
| tree | 5071e204de225fa629490762421970a3b3998d68 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | b3e428e5870e9ed1c667b28c6cbceb8f0fa5d1bd (diff) | |
| download | llvm-a2861db834d909fc4ab3b5e5385ae24024520a97.zip llvm-a2861db834d909fc4ab3b5e5385ae24024520a97.tar.gz llvm-a2861db834d909fc4ab3b5e5385ae24024520a97.tar.bz2 | |
[mips] [IAS] Slightly improve shift instruction generation in expandLoadImm.
Summary:
Generate one DSLL32 of 0 instead of two consecutive DSLL of 16.
In order to do this I had to change createLShiftOri's template argument from a bool to an unsigned.
This also gave me the opportunity to rewrite the mips64-expansions.s test, as it was testing the same cases multiple times and skipping over other cases.
It was also somewhat unreadable, as the CHECK lines were grouped in a huge block of text at the beginning of the file.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8974
llvm-svn: 236311
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions