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| author | Sanjay Patel <spatel@rotateright.com> | 2020-09-02 08:09:24 -0400 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2020-09-02 08:11:36 -0400 |
| commit | 8fb055932c085da21f3b721995a06f42006744bd (patch) | |
| tree | 30f6567c0940f4c387a16626c607213546b5a009 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | c4a2a1307484cffe94a291c42572775411bac8d8 (diff) | |
| download | llvm-8fb055932c085da21f3b721995a06f42006744bd.zip llvm-8fb055932c085da21f3b721995a06f42006744bd.tar.gz llvm-8fb055932c085da21f3b721995a06f42006744bd.tar.bz2 | |
[VectorCombine] allow vector loads with mismatched insert type
This is an enhancement to D81766 to allow loading the minimum target
vector type into an IR vector with a different number of elements.
In one of the motivating tests from PR16739, SLP creates <2 x float>
load ops mixed with <4 x float> insert ops, so we want to handle that
pattern in addition to potential oversized vectors created by the
vectorizers.
For now, we are assuming the insert/extract subvector with undef is
free because there is no exact corresponding TTI modeling for that.
Differential Revision: https://reviews.llvm.org/D86160
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions