diff options
author | John Brawn <john.brawn@arm.com> | 2025-09-16 11:46:54 +0100 |
---|---|---|
committer | GitHub <noreply@github.com> | 2025-09-16 11:46:54 +0100 |
commit | 8fab81121ebd047274f3171eb2902cb564b3e377 (patch) | |
tree | 91d41c846271f448ac9574447379f42238e9cc67 /clang/lib/Frontend/CompilerInvocation.cpp | |
parent | aa1a6948467362a97f2bf10772a491938b20534c (diff) | |
download | llvm-8fab81121ebd047274f3171eb2902cb564b3e377.zip llvm-8fab81121ebd047274f3171eb2902cb564b3e377.tar.gz llvm-8fab81121ebd047274f3171eb2902cb564b3e377.tar.bz2 |
[LSR] Add an addressing mode that considers all addressing modes (#158110)
The way that loops strength reduction works is that the target has to
upfront decide whether it wants its addressing to be preindex,
postindex, or neither. This choice affects:
* Which potential solutions we generate
* Whether we consider a pre/post index load/store as costing an AddRec
or not.
None of these choices are a good fit for either AArch64 or ARM, where
both preindex and postindex addressing are typically free:
* If we pick None then we count pre/post index addressing as costing one
addrec more than is correct so we don't pick them when we should.
* If we pick PreIndexed or PostIndexed then we get the correct cost for
that addressing type, but still get it wrong for the other and also
exclude potential solutions using offset addressing that could have less
cost.
This patch adds an "all" addressing mode that causes all potential
solutions to be generated and counts both pre and postindex as having
AddRecCost of zero. Unfortuntely this reveals problems elsewhere in how
we calculate the cost of things that need to be fixed before we can make
use of it.
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions