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| author | Amara Emerson <aemerson@apple.com> | 2019-03-04 19:16:00 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-03-04 19:16:00 +0000 |
| commit | 8acb0d9c82ed49512ba2df6e4a0e3ee65a220fdf (patch) | |
| tree | 282b6336419bda3f1510960aabf1d156f641f8e3 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 05e233507697ab81007a6b48728add2ee4627e5b (diff) | |
| download | llvm-8acb0d9c82ed49512ba2df6e4a0e3ee65a220fdf.zip llvm-8acb0d9c82ed49512ba2df6e4a0e3ee65a220fdf.tar.gz llvm-8acb0d9c82ed49512ba2df6e4a0e3ee65a220fdf.tar.bz2 | |
Re-commit r355104: "[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1."
The code to materialize a mask from a constant pool load tried to use a 128 bit
LDR to load a 64 bit constant pool entry, which was 8 byte aligned. This resulted
in a link failure in the NEON tests in the test suite since the LDR address was
unaligned. This change fixes that to instead emit a 64 bit LDR if the entry is
64 bit, before converting back to a 128 bit register for the TBL.
llvm-svn: 355326
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions