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| author | Craig Topper <craig.topper@sifive.com> | 2020-11-05 15:44:49 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2020-11-05 16:15:25 -0800 |
| commit | 741b04b0b7912611a8a5b7e74462e87b8930a116 (patch) | |
| tree | ffe63d3151d7825aab77880f4df3d13cde11032e /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 0e3532da98c5aa62582eee9cca07aaf5844b0b90 (diff) | |
| download | llvm-741b04b0b7912611a8a5b7e74462e87b8930a116.zip llvm-741b04b0b7912611a8a5b7e74462e87b8930a116.tar.gz llvm-741b04b0b7912611a8a5b7e74462e87b8930a116.tar.bz2 | |
[RISCV] Only enable GPR<->FPR32 bitconvert isel patterns on RV32. NFCI
Bitconvert requires the bitwidth to match on both sides. On RV64
the GPR size is i64 so bitconvert between f32 isn't possible. The
node should never be generated so the pattern won't ever match, but
moving the patterns under IsRV32 makes it more obviously impossible.
It also moves it to a similar location to the patterns for the
custom nodes we use for RV64.
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions