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| author | Craig Topper <craig.topper@intel.com> | 2018-09-28 17:09:51 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-09-28 17:09:51 +0000 |
| commit | 6ad92200672de5a47588a828f6b21a071c0d1dcb (patch) | |
| tree | 23b7d96cda9af0e73dee29e7153a05dd4e5768dd /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | cea130b0e01ce30c97d5a929857623108333e869 (diff) | |
| download | llvm-6ad92200672de5a47588a828f6b21a071c0d1dcb.zip llvm-6ad92200672de5a47588a828f6b21a071c0d1dcb.tar.gz llvm-6ad92200672de5a47588a828f6b21a071c0d1dcb.tar.bz2 | |
[X86] Add the movbe instruction intrinsics from icc.
These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website.
All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics
Differential Revision: https://reviews.llvm.org/D52586
llvm-svn: 343343
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions