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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 13:13:03 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 13:13:03 +0000 |
| commit | 6a803f61621ebcca6f9e1f4244af912cd7fb1540 (patch) | |
| tree | 98008aba18d9a9901ffdaa5bf9c0f2276d278f93 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 0469dbd43fca9215f14a6b17e3b8f59795feb4a6 (diff) | |
| download | llvm-6a803f61621ebcca6f9e1f4244af912cd7fb1540.zip llvm-6a803f61621ebcca6f9e1f4244af912cd7fb1540.tar.gz llvm-6a803f61621ebcca6f9e1f4244af912cd7fb1540.tar.bz2 | |
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.
Summary:
The linked-load, store-conditional operations have been re-encoded such
that have a 9-bit offset instead of the 16-bit offset they have prior to
MIPS32r6/MIPS64r6.
While implementing this, I noticed that the atomic load/store pseudos always
emit a sign extension using sll and sra. I have improved this to use seb/seh
when they are available (MIPS32r2/MIPS64r2 and above).
Depends on D4118
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4119
llvm-svn: 211018
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions