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author | Craig Topper <craig.topper@intel.com> | 2020-02-06 09:42:01 -0800 |
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committer | Craig Topper <craig.topper@intel.com> | 2020-02-06 10:22:24 -0800 |
commit | 600f2e1c4de59a48a765d9ac8eadab2f4307fa30 (patch) | |
tree | 29526aee0de404f1f7d20e14e7abda22fb5f6cc7 /clang/lib/Frontend/CompilerInvocation.cpp | |
parent | 25de3f98b8a7436404dbc185040645f2549a8a8f (diff) | |
download | llvm-600f2e1c4de59a48a765d9ac8eadab2f4307fa30.zip llvm-600f2e1c4de59a48a765d9ac8eadab2f4307fa30.tar.gz llvm-600f2e1c4de59a48a765d9ac8eadab2f4307fa30.tar.bz2 |
[X86] Remove SETB_C8r/SETB_C16r pseudo instructions. Use SETB_C32r and EXTRACT_SUBREG instead.
Only 32 and 64 bit SBB are dependency breaking instructons on some
CPUs. The 8 and 16 bit forms have to preserve upper bits of the GPR.
This patch removes the smaller forms and selects the wider form
instead. I had to do this with custom code as the tblgen generated
code glued the eflags copytoreg to the extract_subreg instead of
to the SETB pseudo.
Longer term I think we can remove X86ISD::SETCC_CARRY and use
(X86ISD::SBB zero, zero). We'll want to keep the pseudo and select
(X86ISD::SBB zero, zero) to either a MOV32r0+SBB for targets where
there is no dependency break and SETB_C32/SETB_C64 for targets
that have a dependency break. May want some way to avoid the MOV32r0
if the instruction that produced the carry flag happened to def a
register that we can use for the dependency.
I think the flag copy lowering should be using NEG instead of SUB to
handle SETB. That would avoid the MOV32r0 there. Or maybe it should
use a ADC with -1 to recreate the carry flag and keep the SETB?
That would avoid a MOVZX on the input of the SUB.
Differential Revision: https://reviews.llvm.org/D74024
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions