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| author | Jay Foad <jay.foad@amd.com> | 2020-10-29 12:10:56 +0000 |
|---|---|---|
| committer | Jay Foad <jay.foad@amd.com> | 2020-10-29 16:00:53 +0000 |
| commit | 58de4b205310d18614eabdcbaa1772e9fc090df3 (patch) | |
| tree | 966efcd8282cbe98ba519a28c3a86ff30d32af16 /clang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 81f7b96ed0a2295e0b82ca185019370ac8e1895e (diff) | |
| download | llvm-58de4b205310d18614eabdcbaa1772e9fc090df3.zip llvm-58de4b205310d18614eabdcbaa1772e9fc090df3.tar.gz llvm-58de4b205310d18614eabdcbaa1772e9fc090df3.tar.bz2 | |
[AMDGPU] Use pseudo instructions for readlane/writelane
This reverts r227987 "R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2".
All the codegen changes are caused by the post-RA scheduler no longer
treating readlane/writelane as scheduling barriers due to having
unmodelled side effects. (The pseudos are hasSideEffects = 0, but the
real instructions are hasSideEffects = ? which TableGen conservatively
treats as 1.)
Differential Revision: https://reviews.llvm.org/D90401
Diffstat (limited to 'clang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions