diff options
| author | Craig Topper <craig.topper@intel.com> | 2020-02-03 17:57:12 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-02-03 17:57:48 -0800 |
| commit | c7768ce52224297fd5d39e8dae69cf6b0df4ece1 (patch) | |
| tree | 838ccb8b4c32ca7bd6c958c25a3f6e5b0d28f419 /clang/lib/Frontend/ASTMerge.cpp | |
| parent | 9a40670a0a4e9a3139bd082c9e48ae47b2cb876f (diff) | |
| download | llvm-c7768ce52224297fd5d39e8dae69cf6b0df4ece1.zip llvm-c7768ce52224297fd5d39e8dae69cf6b0df4ece1.tar.gz llvm-c7768ce52224297fd5d39e8dae69cf6b0df4ece1.tar.bz2 | |
[X86] Update the haswell and broadwell scheduler information for gather instructions
Broadwell was missing half the gather instructions. Both models
had some mixups in the resource costs and number of uops.
I've updated here based on what I think the original IACA source
says with some cross checking against the microcode.
I'm not sure about latency as the IACA source I have doesn't have
that information. So I'm using the latency from uops.info.
I plan to update Skylake models as well, but I'll do that in a
separate patch.
Differential Revision: https://reviews.llvm.org/D73844
Diffstat (limited to 'clang/lib/Frontend/ASTMerge.cpp')
0 files changed, 0 insertions, 0 deletions