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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-01 13:22:07 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-01 13:22:07 +0000 |
| commit | 9f992c238abb34ead73318633da38f80153eef2d (patch) | |
| tree | 06598f705c5b7ee5ed4d28fdd4bcb85a570de7c5 /clang/lib/Frontend/ASTMerge.cpp | |
| parent | 5dafcb9b1184478228b669327d17a5bc990efe0c (diff) | |
| download | llvm-9f992c238abb34ead73318633da38f80153eef2d.zip llvm-9f992c238abb34ead73318633da38f80153eef2d.tar.gz llvm-9f992c238abb34ead73318633da38f80153eef2d.tar.bz2 | |
AMDGPU/GlobalISel: Fix scc->vcc copy handling
This was checking the size of the register with the value of the size,
which happens to be exec. Also fix assuming VCC is 64-bit to fix
wave32.
Also remove some untested handling for physical registers which is
skipped. This doesn't insert the V_CNDMASK_B32 if SCC is the physical
copy source. I'm not sure if this should be trying to handle this
special case instead of dealing with this in copyPhysReg.
llvm-svn: 364761
Diffstat (limited to 'clang/lib/Frontend/ASTMerge.cpp')
0 files changed, 0 insertions, 0 deletions