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| author | Craig Topper <craig.topper@sifive.com> | 2025-09-30 19:14:30 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-30 19:14:30 -0700 |
| commit | 3e1d4d4144cc9d28ccd85cf49d6fc836c38ffbaa (patch) | |
| tree | dfe0bd00d0d26a156c83288b48afa7dd83d2138a /clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp | |
| parent | d392563433316e310edacf35a40fb2f9aa477acc (diff) | |
| download | llvm-3e1d4d4144cc9d28ccd85cf49d6fc836c38ffbaa.zip llvm-3e1d4d4144cc9d28ccd85cf49d6fc836c38ffbaa.tar.gz llvm-3e1d4d4144cc9d28ccd85cf49d6fc836c38ffbaa.tar.bz2 | |
[RISCV] Remove Zicntr from sifive-p450/p470/p670. (#161444)
These cores don't implement the `time` CSR. They require SBI to trap and
emulate it which is allowed by RVA20U.
Diffstat (limited to 'clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp')
0 files changed, 0 insertions, 0 deletions