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| author | David Green <david.green@arm.com> | 2020-10-30 13:34:27 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2020-10-30 13:34:27 +0000 |
| commit | d14db8c8dc980196c8847d109bd2e585c2ffeb73 (patch) | |
| tree | e237c88b86762f9356e18bd1b977979cc98d7bab /clang/lib/CodeGen/TargetInfo.cpp | |
| parent | 62286c569d84c81236522c386a67e60f8f333f63 (diff) | |
| download | llvm-d14db8c8dc980196c8847d109bd2e585c2ffeb73.zip llvm-d14db8c8dc980196c8847d109bd2e585c2ffeb73.tar.gz llvm-d14db8c8dc980196c8847d109bd2e585c2ffeb73.tar.bz2 | |
[ARM] Match MVE vqdmulh
This adds ISel matching for a form of VQDMULH. There are several ir
patterns that we could match to that instruction, this one is for:
min(ashr(mul(sext(a), sext(b)), 7), 127)
Which is what llvm will optimize to once it has removed the max that
usually makes up the min/max saturate pattern, as in this case the
compare will always be false. The additional complication to match i32
patterns (which extend into an i64) is that the min will be a
vselect/setcc, as vmin is not supported for i64 vectors. Tablegen
patterns have also been updated to attempt to reuse the MVE_TwoOpPattern
patterns.
Differential Revision: https://reviews.llvm.org/D90096
Diffstat (limited to 'clang/lib/CodeGen/TargetInfo.cpp')
0 files changed, 0 insertions, 0 deletions