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| author | Zvi Rackover <zvi.rackover@intel.com> | 2017-01-05 15:11:43 +0000 |
|---|---|---|
| committer | Zvi Rackover <zvi.rackover@intel.com> | 2017-01-05 15:11:43 +0000 |
| commit | 4b7d724d625dcae2466c2bb68a87a0a138fe281b (patch) | |
| tree | dd4cd90b4023aafa598c4db00d02c53051cb2d82 /clang/lib/CodeGen/ObjectFilePCHContainerOperations.cpp | |
| parent | 2b6038458150b22fa2d4d802d8340a217e0c20c1 (diff) | |
| download | llvm-4b7d724d625dcae2466c2bb68a87a0a138fe281b.zip llvm-4b7d724d625dcae2466c2bb68a87a0a138fe281b.tar.gz llvm-4b7d724d625dcae2466c2bb68a87a0a138fe281b.tar.bz2 | |
[X86] Optimize vector shifts with variable but uniform shift amounts
Summary:
For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register.
The lower 64-bits of the register are evaluated to determine the shift amount.
This patch improves the construction of the vector containing the shift amount.
Reviewers: craig.topper, delena, RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D28353
llvm-svn: 291120
Diffstat (limited to 'clang/lib/CodeGen/ObjectFilePCHContainerOperations.cpp')
0 files changed, 0 insertions, 0 deletions