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| author | David Green <david.green@arm.com> | 2025-06-21 07:01:35 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-06-21 07:01:35 +0100 |
| commit | 1fec092fd74abc6fa7399da5bcf165d6249883f5 (patch) | |
| tree | 35e80e63f85a577316ac493a94c4265d342a7454 /clang/lib/CodeGen/ModuleBuilder.cpp | |
| parent | cb4f329004b8fc346bbd44ae8f9b94ff2e41998b (diff) | |
| download | llvm-1fec092fd74abc6fa7399da5bcf165d6249883f5.zip llvm-1fec092fd74abc6fa7399da5bcf165d6249883f5.tar.gz llvm-1fec092fd74abc6fa7399da5bcf165d6249883f5.tar.bz2 | |
[AArch64][GlobalISel] Allow selecting FPR index loads. (#143835)
We can, through legalization of certain operations, end up generating
G_INDEXED_LOAD into FPR registers that require entensions. SExt and ZExt
will always opt for GPR, but anyext/noext can curently be set to FPR
registers in regbankselect. As writing a subregister will set higher
bits in the same register to 0, we can successfully handle zext and
anyext on FPR registers, which is what this patch attempts to add.
Diffstat (limited to 'clang/lib/CodeGen/ModuleBuilder.cpp')
0 files changed, 0 insertions, 0 deletions