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| author | Craig Topper <craig.topper@sifive.com> | 2025-04-24 12:14:05 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-24 12:14:05 -0700 |
| commit | f261f1406d4870410d3c9e61903e65ffd427d8ec (patch) | |
| tree | 5adf278490ef58842fed795c66f806c74c7e3829 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | c8dc3ed9c464580273c2d91b8ec769d4f0193a1b (diff) | |
| download | llvm-f261f1406d4870410d3c9e61903e65ffd427d8ec.zip llvm-f261f1406d4870410d3c9e61903e65ffd427d8ec.tar.gz llvm-f261f1406d4870410d3c9e61903e65ffd427d8ec.tar.bz2 | |
[SelectionDAG][RISCV] Teach computeKnownBits to use range metadata for atomic_load. (#137119)
And teach SelectionDAGBuilder to get the range metadata in
visitAtomicLoad.
This allows us to recognize that sign extending a byte load of a
boolean value from memory will produce zeros for the extended bits.
This allow us to remove an AND on RISC-V.
Tests copied from #136502 with range metadata added to i1 cases.
Some of the test effects overlap with #136502, but that patch can't
handle the acquire or seq_cst cases with the Zalasr extension. We
only have sign extending versions of those loads.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions