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| author | Brox Chen <guochen2@amd.com> | 2025-02-25 17:09:34 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-25 17:09:34 -0500 |
| commit | e6f6a1e863895a3378e703525a6d0d293413be33 (patch) | |
| tree | b2d95e0bf234769d09304a8bd8805ad48e0436cb /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 59cee030fb9b8be7ee0a89964ead5120d029deb4 (diff) | |
| download | llvm-e6f6a1e863895a3378e703525a6d0d293413be33.zip llvm-e6f6a1e863895a3378e703525a6d0d293413be33.tar.gz llvm-e6f6a1e863895a3378e703525a6d0d293413be33.tar.bz2 | |
[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)
Enable gisel selection for uaddsat and usubsat in true16 flow
This patch includes:
1. Added VGPR_16_Lo128/VGPR_16 to register bank and update register info
for recognizing 16bit regclass id and bit width
2. uaddsat/usubsat test update
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions