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| author | Jim Lin <jim@andestech.com> | 2024-10-14 10:47:59 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-14 10:47:59 +0800 |
| commit | dba54fb074af1573984807e23640a202e0984a56 (patch) | |
| tree | 254f57cf30388fddab1788ec145dd3f544facd1f /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | cd12ffb622df5392020d0793e3fff7c3bf8385a2 (diff) | |
| download | llvm-dba54fb074af1573984807e23640a202e0984a56.zip llvm-dba54fb074af1573984807e23640a202e0984a56.tar.gz llvm-dba54fb074af1573984807e23640a202e0984a56.tar.bz2 | |
[RISCV] Add support for inline asm constraint vd (#111653)
It constrains vector registers excluding v0. Refer to
https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html RISC-V part.
This patch also adds a testcase for constraints vr, vd and vm.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions