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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-09-13 10:10:59 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-13 10:10:59 +0900 |
| commit | 9af4a854602804430dc04766ce1be311259707d6 (patch) | |
| tree | bac2bca8e95b98c33a378488f4433288f57c05af /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | ba3b3e3ac812ae30f12f92ee8c4a1c668cd9817e (diff) | |
| download | llvm-9af4a854602804430dc04766ce1be311259707d6.zip llvm-9af4a854602804430dc04766ce1be311259707d6.tar.gz llvm-9af4a854602804430dc04766ce1be311259707d6.tar.bz2 | |
AMDGPU: Add test which shows unnecessary register alignment (#158168)
The b96 tr loads are a special case that does not require even
aligned VGPRs
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions