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| author | Pengcheng Wang <wangpengcheng.pp@bytedance.com> | 2025-05-13 19:05:42 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-13 19:05:42 +0800 |
| commit | 9570bf978d77aa53fffb50c60388da8f1bd71e4c (patch) | |
| tree | 6a517266664a9ed50af6380cc55e6ed87f8dad8f /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | c14acb74423a577e10bbb635109851742e77444f (diff) | |
| download | llvm-9570bf978d77aa53fffb50c60388da8f1bd71e4c.zip llvm-9570bf978d77aa53fffb50c60388da8f1bd71e4c.tar.gz llvm-9570bf978d77aa53fffb50c60388da8f1bd71e4c.tar.bz2 | |
[TableGen][MacroFusion] Predicate if the first inst has the same register (#137778)
We rename `SameReg` to `SecondInstHasSameReg ` and add
`FirstInstHasSameReg `
which has the logic but applies to the first instruction.
We have some cases that require the first instruction has the same
input/output register.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions