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| author | Chad Rosier <mcrosier@codeaurora.org> | 2015-09-03 18:13:57 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2015-09-03 18:13:57 +0000 |
| commit | 6c36eff1d6213e1bc595b37806c193cd5b6dac0e (patch) | |
| tree | 849e8e42891e928c5c08a51bccc9bb3004f04330 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 4410b22cea32bf55e13404745dd51063c0d9fb8e (diff) | |
| download | llvm-6c36eff1d6213e1bc595b37806c193cd5b6dac0e.zip llvm-6c36eff1d6213e1bc595b37806c193cd5b6dac0e.tar.gz llvm-6c36eff1d6213e1bc595b37806c193cd5b6dac0e.tar.bz2 | |
[AArch64] Improve ISel using across lane addition reduction.
In vectorized add reduction code, the final "reduce" step is sub-optimal.
This change wll combine :
ext v1.16b, v0.16b, v0.16b, #8
add v0.4s, v1.4s, v0.4s
dup v1.4s, v0.s[1]
add v0.4s, v1.4s, v0.4s
into
addv s0, v0.4s
PR21371
http://reviews.llvm.org/D12325
Patch by Jun Bum Lim <junbuml@codeaurora.org>!
llvm-svn: 246790
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions