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| author | Sanjay Patel <spatel@rotateright.com> | 2016-07-08 21:17:51 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-07-08 21:17:51 +0000 |
| commit | 664514f7fe1451c5a41e871e6174677f941c9548 (patch) | |
| tree | 5fdfed3f16f12f035bf56ccab8e25adb9961f37b /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 68f499a6fa5e3b52b08f920f61d6f73f9aa57bcf (diff) | |
| download | llvm-664514f7fe1451c5a41e871e6174677f941c9548.zip llvm-664514f7fe1451c5a41e871e6174677f941c9548.tar.gz llvm-664514f7fe1451c5a41e871e6174677f941c9548.tar.bz2 | |
[InstCombine] don't form select from bitcasted logic ops if bitcasts have >1 use
This isn't a sure thing (are 2 extra bitcasts less expensive than a logic op?),
but we'll try to err on the conservative side by going with the case that has
less IR instructions.
Note: This question came up in http://reviews.llvm.org/D22114 , but this part is
independent of that patch proposal, so I'm making this small change ahead of that
one.
See also:
http://reviews.llvm.org/rL274926
llvm-svn: 274932
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions