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| author | Min-Yih Hsu <min.hsu@sifive.com> | 2025-02-05 15:30:33 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-05 15:30:33 -0800 |
| commit | 5a1e16f6de26c21cdfae1de05bd075d57029a3e1 (patch) | |
| tree | d5d947b2d247267e4c7414377ab3913aa5067357 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 1901f4ac8eb1ddd8df822841a48b818c496aa2ad (diff) | |
| download | llvm-5a1e16f6de26c21cdfae1de05bd075d57029a3e1.zip llvm-5a1e16f6de26c21cdfae1de05bd075d57029a3e1.tar.gz llvm-5a1e16f6de26c21cdfae1de05bd075d57029a3e1.tar.bz2 | |
[IR][RISCV] Add llvm.vector.(de)interleave3/5/7 (#124825)
These three intrinsics are similar to llvm.vector.(de)interleave2 but
work with 3/5/7 vector operands or results.
For RISC-V, it's important to have them in order to support segmented
load/store with factor of 2 to 8: factor of 2/4/8 can be synthesized
from (de)interleave2; factor of 6 can be synthesized from factor of 2
and 3; factor 5 and 7 have their own intrinsics added by this patch.
This patch only adds codegen support for these intrinsics, we still need
to teach vectorizer to generate them as well as teaching
InterleavedAccessPass to use them.
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Co-authored-by: Craig Topper <craig.topper@sifive.com>
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions