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| author | Craig Topper <craig.topper@sifive.com> | 2025-02-25 10:04:57 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-25 10:04:57 -0800 |
| commit | 4f18f3f09a744ddd05de2188592fa11533ff3054 (patch) | |
| tree | 0a0c0b77a188f18c4fd10dcc096be0724901a6b1 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 48db4e8377f8504cf151cf4d2b4ecf33461eedc8 (diff) | |
| download | llvm-4f18f3f09a744ddd05de2188592fa11533ff3054.zip llvm-4f18f3f09a744ddd05de2188592fa11533ff3054.tar.gz llvm-4f18f3f09a744ddd05de2188592fa11533ff3054.tar.bz2 | |
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
We prefer to emit addi instead of ori because its more compressible, but
this can pessimize the sext.w removal pass.
If the input to the OR is known to be a sign extended 32 bit value, we
can use addiw instead of addi which will give more power to the sext.w
removal pass. As it is known to produce sign a sign extended value and
only consume the lower 32 bits.
Fixes #128468.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
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