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| author | Min-Yih Hsu <min.hsu@sifive.com> | 2025-10-07 15:20:30 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-07 15:20:30 -0700 |
| commit | 198f29469a159e8418734e18edb60e33cb476462 (patch) | |
| tree | 5a76de1eb5d611ce818c722eafc60410213cc233 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 57b5ba00cb421b9be17bac10036763f42fbe9298 (diff) | |
| download | llvm-198f29469a159e8418734e18edb60e33cb476462.zip llvm-198f29469a159e8418734e18edb60e33cb476462.tar.gz llvm-198f29469a159e8418734e18edb60e33cb476462.tar.bz2 | |
[RISCV] Add missing vector floating point scheduling model tests for SiFive7 (#162386)
This is helpful on validating the non-throttled vector FP64 performance,
compared to the throttled model of sifive-x390.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions