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| author | Anton Sidorenko <anton.sidorenko@syntacore.com> | 2024-09-17 18:52:55 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-17 18:52:55 +0300 |
| commit | 09fc1781807b46e2c6a92e744e70a1ffb530c3ad (patch) | |
| tree | 36f244b67cd7ff3e762996be46dfabfdfbdc551e /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 594579b7af82dab786bb75786451ca582543a697 (diff) | |
| download | llvm-09fc1781807b46e2c6a92e744e70a1ffb530c3ad.zip llvm-09fc1781807b46e2c6a92e744e70a1ffb530c3ad.tar.gz llvm-09fc1781807b46e2c6a92e744e70a1ffb530c3ad.tar.bz2 | |
[RISCV] Add scheduling model for Syntacore SCR7 (#108814)
Syntacore SCR7 is rv64imafdcv_zba_zbb_zbc_zbs_zkn.
Scheduling model for RVV will be added later.
Overview: https://syntacore.com/products/scr7
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Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev@syntacore.com>
Co-authored-by: Elena Lepilkina <elena.lepilkina@syntacore.com>
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
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