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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-29 18:51:54 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-29 18:51:54 +0000 |
| commit | 0040f18256689127d41186b98ceea0c2b3eb3550 (patch) | |
| tree | bfa127bc079571e56b575e72feeaa5a52a6382f2 /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 4e673c95fb04006508af0dc690dc84062bc9f556 (diff) | |
| download | llvm-0040f18256689127d41186b98ceea0c2b3eb3550.zip llvm-0040f18256689127d41186b98ceea0c2b3eb3550.tar.gz llvm-0040f18256689127d41186b98ceea0c2b3eb3550.tar.bz2 | |
R600/SI: Set bits on SMRD instructions
Set mayStore = 0 and enable named operand table.
llvm-svn: 214194
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions