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author | Simon Tatham <simon.tatham@arm.com> | 2020-03-11 12:48:36 +0000 |
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committer | Simon Tatham <simon.tatham@arm.com> | 2020-03-18 10:55:04 +0000 |
commit | 28c5d97beec7a2582869f992f54a178c805e2e51 (patch) | |
tree | 1ec391d15b9a283f5c82ec7ed5966a4b82cddc2e /clang/lib/CodeGen/CodeGenFunction.h | |
parent | 8d019cda851a1031fbce3c50be0975438147f11d (diff) | |
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[ARM,MVE] Add intrinsics and isel for MVE integer VMLA.
Summary:
These instructions compute multiply+add in integers, with one of the
operands being a splat of a scalar. (VMLA and VMLAS differ in whether
the splat operand is a multiplier or the addend.)
I've represented these in IR using existing standard IR operations for
the unpredicated forms. The predicated forms are done with target-
specific intrinsics, as usual.
When operating on n-bit vector lanes, only the bottom n bits of the
i32 scalar operand are used. So we have to tell that to isel lowering,
to allow it to remove a pointless sign- or zero-extension instruction
on that input register. That's done in `PerformIntrinsicCombine`, but
first I had to enable `PerformIntrinsicCombine` for MVE targets
(previously all the intrinsics it handled were for NEON), and make it
a method of `ARMTargetLowering` so that it can get at
`SimplifyDemandedBits`.
Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D76122
Diffstat (limited to 'clang/lib/CodeGen/CodeGenFunction.h')
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