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| author | Pravin Jagtap <Pravin.Jagtap@amd.com> | 2025-01-31 12:23:48 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-31 12:23:48 +0530 |
| commit | e6d16f93b329f2f9618d18d0b99c6060e206cf08 (patch) | |
| tree | 4c3157d3a0335b5e44d16bd7bd825f62aa532ac8 /clang/lib/CodeGen/CodeGenFunction.cpp | |
| parent | 51b123078e64d73f7d8db78645d6f56fbed3215d (diff) | |
| download | llvm-e6d16f93b329f2f9618d18d0b99c6060e206cf08.zip llvm-e6d16f93b329f2f9618d18d0b99c6060e206cf08.tar.gz llvm-e6d16f93b329f2f9618d18d0b99c6060e206cf08.tar.bz2 | |
[AMDGPU] Allow unaligned VGPR for ds_read_b96_tr_b6 (#125169)
All load transpose instructions follow gfx950 standard of even aligned
VGPR except ds_read_b96_tr_b6, which allows unaligned VGPR.
Co-authored-by: Sirish Pande
[Sirish.Pande@amd.com](mailto:Sirish.Pande@amd.com)
Diffstat (limited to 'clang/lib/CodeGen/CodeGenFunction.cpp')
0 files changed, 0 insertions, 0 deletions