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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-09-03 11:10:51 +0100 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-09-03 11:10:51 +0100 |
| commit | bd956b7db398e4ec1a73a3b344a304d6c6630681 (patch) | |
| tree | 3a874910c3aae3f9a1ce3ad8c28eeae75e47a765 /clang/lib/CodeGen/CodeGenFunction.cpp | |
| parent | 0735200e3f50de1cab4d2fff0ebff9aec52ff074 (diff) | |
| download | llvm-bd956b7db398e4ec1a73a3b344a304d6c6630681.zip llvm-bd956b7db398e4ec1a73a3b344a304d6c6630681.tar.gz llvm-bd956b7db398e4ec1a73a3b344a304d6c6630681.tar.bz2 | |
[X86] Fix fmul throughput/latency/uops counts
Matches numbers from AMD SoG + Agner - should always be on FPU Pipes 0+1, no additional uops for folded instructions and znver1 double pumps 256-bit vectors and is always latency = 4cy for f64 multiplies
Noticed while adding fmul CostKinds support to the x86 cost models in rG0735200e3f50 and znver1 wasn't being flagged as requiring 2uop for 256-bit vectors
Diffstat (limited to 'clang/lib/CodeGen/CodeGenFunction.cpp')
0 files changed, 0 insertions, 0 deletions