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| author | Craig Topper <craig.topper@intel.com> | 2020-10-03 16:55:18 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-10-03 16:55:19 -0700 |
| commit | adccc0bfa301005367d6b89a3aacc07ef0166e64 (patch) | |
| tree | d200afb9f8a6beb46d1d2bfce5bea0f9ebcee701 /clang/lib/CodeGen/CodeGenFunction.cpp | |
| parent | 9b851527d53345c4a5d56a909dfa1ca7f59a0c11 (diff) | |
| download | llvm-adccc0bfa301005367d6b89a3aacc07ef0166e64.zip llvm-adccc0bfa301005367d6b89a3aacc07ef0166e64.tar.gz llvm-adccc0bfa301005367d6b89a3aacc07ef0166e64.tar.bz2 | |
[X86] Add X86ISD opcodes for the Key Locker AESENC*KL and AESDEC*KL instructions
Instead of emitting MachineSDNodes during lowering, emit X86ISD
opcodes. These opcodes will either be selected by tablegen
patterns or custom selection code.
Emitting MachineSDNodes during lowering is uncommon so this makes
things more consistent. It also allows selectAddr to be called to
perform address matching during instruction selection.
I had trouble getting tablegen to accept XMM0-XMM7 as results in
an isel pattern for the WIDE instructions so I had to use custom
instruction selection.
Diffstat (limited to 'clang/lib/CodeGen/CodeGenFunction.cpp')
0 files changed, 0 insertions, 0 deletions