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| author | Jessica Clarke <jrtc27@jrtc27.com> | 2021-07-29 16:53:27 +0100 |
|---|---|---|
| committer | Jessica Clarke <jrtc27@jrtc27.com> | 2021-07-29 16:53:29 +0100 |
| commit | 95ef464ac9d1972953709c57449ac178771cd221 (patch) | |
| tree | 41aaf2885fd0f0b5306fb7cc48c3071a0940f9fe /clang/lib/CodeGen/CodeGenFunction.cpp | |
| parent | 9a5bc83660ed6978521dcfa4faac140cf5b2e895 (diff) | |
| download | llvm-95ef464ac9d1972953709c57449ac178771cd221.zip llvm-95ef464ac9d1972953709c57449ac178771cd221.tar.gz llvm-95ef464ac9d1972953709c57449ac178771cd221.tar.bz2 | |
Handle subregs and superregs in callee-saved register mask
If a target lists both a subreg and a superreg in a callee-saved
register mask, the prolog will spill both aliasing registers. Instead,
don't spill the subreg if a superreg is being spilled. This case is hit by the
PowerPC SPE code, as well as a modified RISC-V backend for CHERI I maintain out
of tree.
Reviewed By: jhibbits
Differential Revision: https://reviews.llvm.org/D73170
Diffstat (limited to 'clang/lib/CodeGen/CodeGenFunction.cpp')
0 files changed, 0 insertions, 0 deletions