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| author | Shengchen Kan <shengchen.kan@intel.com> | 2023-05-19 13:26:45 +0800 |
|---|---|---|
| committer | Shengchen Kan <shengchen.kan@intel.com> | 2023-05-19 18:22:30 +0800 |
| commit | 5586bc539acb26cb94e461438de01a5080513401 (patch) | |
| tree | 22d95f335fb35164b4e813acd0899063971bb9aa /clang/lib/CodeGen/CodeGenFunction.cpp | |
| parent | 91a7aa4c9b29fa217f45badeaa87c4667a28f807 (diff) | |
| download | llvm-5586bc539acb26cb94e461438de01a5080513401.zip llvm-5586bc539acb26cb94e461438de01a5080513401.tar.gz llvm-5586bc539acb26cb94e461438de01a5080513401.tar.bz2 | |
[X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize during MC lowering, NFCI
This is follow-up of D150107.
In addition, the function `X86::optimizeToFixedRegisterOrShortImmediateForm` can be
shared with project bolt and eliminates the code in X86InstrRelaxTables.cpp.
Differential Revision: https://reviews.llvm.org/D150949
Diffstat (limited to 'clang/lib/CodeGen/CodeGenFunction.cpp')
0 files changed, 0 insertions, 0 deletions