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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-09-03 18:45:04 +0100 |
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| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-09-03 18:45:08 +0100 |
| commit | 444685de06e0e8257aa913b198e2a185ff8ba7f5 (patch) | |
| tree | f3383d5c37261ca73f3cb9bab8bb6950e2de6a87 /clang/lib/CodeGen/CodeGenFunction.cpp | |
| parent | 114b7762a99677c021d7cf461fbc7ca796d0b76d (diff) | |
| download | llvm-444685de06e0e8257aa913b198e2a185ff8ba7f5.zip llvm-444685de06e0e8257aa913b198e2a185ff8ba7f5.tar.gz llvm-444685de06e0e8257aa913b198e2a185ff8ba7f5.tar.bz2 | |
[CostModel][X86] Adjust mul v4i32/v8i32 throughput cost
Based off the numbers from AMD SoG + Agner - vXi32 are both half-rate, and znver1 double-pumps the v8i32 op
We should have caught this earlier as many Intel models have half-rate pmulld already :-(
Diffstat (limited to 'clang/lib/CodeGen/CodeGenFunction.cpp')
0 files changed, 0 insertions, 0 deletions